`timescale 1ns/1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:47:33 04/20/2009 
// Design Name: 
// Module Name:    piperegPC 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module piperegPC(clk, in, out,reset);
    input clk,reset;
    input [31:0] in;
    output [31:0] out;

reg [31:0] out;

always @ (posedge clk )
begin
	if(reset)
		out = 0;
	else
		out = in;
end
endmodule
